|host_2191
CLOCK => latched_cs.CLK
CLOCK => latched_wr.CLK
CLOCK => latched_rd.CLK
CLOCK => rising_edge:U5.i_clock
CLOCK => watchdog:U4.i_clock
CLOCK => hp_sm:U3.i_clock
CLOCK => ep_sm:U2.i_clock
CLOCK => latched_hack.CLK
RESET => system_reset.IN0
ERROR <= watchdog:U4.o_error
ADDRESS[0] => hp_sm:U3.i_host_cycle
ADDRESS[0] => data_path:U1.i_address[0]
ADDRESS[1] => data_path:U1.i_address[1]
ADDRESS[2] => hp_sm:U3.i_host_mem_sel
ADDRESS[2] => data_path:U1.i_address[2]
ADDRESS[3] => data_path:U1.i_address[3]
DATA[0] <= data_path:U1.io_data[0]
DATA[1] <= data_path:U1.io_data[1]
DATA[2] <= data_path:U1.io_data[2]
DATA[3] <= data_path:U1.io_data[3]
DATA[4] <= data_path:U1.io_data[4]
DATA[5] <= data_path:U1.io_data[5]
DATA[6] <= data_path:U1.io_data[6]
DATA[7] <= data_path:U1.io_data[7]
DATA[8] <= data_path:U1.io_data[8]
DATA[9] <= data_path:U1.io_data[9]
DATA[10] <= data_path:U1.io_data[10]
DATA[11] <= data_path:U1.io_data[11]
DATA[12] <= data_path:U1.io_data[12]
DATA[13] <= data_path:U1.io_data[13]
DATA[14] <= data_path:U1.io_data[14]
DATA[15] <= data_path:U1.io_data[15]
CS => latched_cs.DATAIN
WR => latched_wr.DATAIN
RD => latched_rd.DATAIN
ACK <= ep_sm:U2.o_ack
HACK => latched_hack.DATAIN
HAD[0] <= data_path:U1.io_had[0]
HAD[1] <= data_path:U1.io_had[1]
HAD[2] <= data_path:U1.io_had[2]
HAD[3] <= data_path:U1.io_had[3]
HAD[4] <= data_path:U1.io_had[4]
HAD[5] <= data_path:U1.io_had[5]
HAD[6] <= data_path:U1.io_had[6]
HAD[7] <= data_path:U1.io_had[7]
HAD[8] <= data_path:U1.io_had[8]
HAD[9] <= data_path:U1.io_had[9]
HAD[10] <= data_path:U1.io_had[10]
HAD[11] <= data_path:U1.io_had[11]
HAD[12] <= data_path:U1.io_had[12]
HAD[13] <= data_path:U1.io_had[13]
HAD[14] <= data_path:U1.io_had[14]
HAD[15] <= data_path:U1.io_had[15]
HA16 <= data_path:U1.o_ha16
HCMS <= hp_sm:U3.o_hcms
HCIOMS <= hp_sm:U3.o_hcioms
HALE <= hp_sm:U3.o_hale
HWR <= hp_sm:U3.o_hwr
HRD <= hp_sm:U3.o_hrd


|host_2191|data_path:U1
i_reset => i~0.IN0
i_reset => i~77.OUTPUTSELECT
i_reset => temp_buffer[15].OUTPUTSELECT
i_reset => temp_buffer[14].OUTPUTSELECT
i_reset => temp_buffer[13].OUTPUTSELECT
i_reset => temp_buffer[12].OUTPUTSELECT
i_reset => temp_buffer[11].OUTPUTSELECT
i_reset => temp_buffer[10].OUTPUTSELECT
i_reset => temp_buffer[9].OUTPUTSELECT
i_reset => temp_buffer[8].OUTPUTSELECT
i_reset => temp_buffer[7].OUTPUTSELECT
i_reset => temp_buffer[6].OUTPUTSELECT
i_reset => temp_buffer[5].OUTPUTSELECT
i_reset => temp_buffer[4].OUTPUTSELECT
i_reset => temp_buffer[3].OUTPUTSELECT
i_reset => temp_buffer[2].OUTPUTSELECT
i_reset => temp_buffer[1].OUTPUTSELECT
i_reset => temp_buffer[0].OUTPUTSELECT
i_latch_had => i~4.OUTPUTSELECT
i_latch_had => i~5.OUTPUTSELECT
i_latch_had => i~6.OUTPUTSELECT
i_latch_had => i~7.OUTPUTSELECT
i_latch_had => i~8.OUTPUTSELECT
i_latch_had => i~9.OUTPUTSELECT
i_latch_had => i~10.OUTPUTSELECT
i_latch_had => i~11.OUTPUTSELECT
i_latch_had => i~12.OUTPUTSELECT
i_latch_had => i~13.OUTPUTSELECT
i_latch_had => i~14.OUTPUTSELECT
i_latch_had => i~15.OUTPUTSELECT
i_latch_had => i~16.OUTPUTSELECT
i_latch_had => i~17.OUTPUTSELECT
i_latch_had => i~18.OUTPUTSELECT
i_latch_had => i~19.OUTPUTSELECT
i_latch_had => i~20.IN0
o_valid_hp_access <= i~78.DB_MAX_OUTPUT_PORT_TYPE
io_data[0] <= i~95
io_data[1] <= i~94
io_data[2] <= i~93
io_data[3] <= i~92
io_data[4] <= i~91
io_data[5] <= i~90
io_data[6] <= i~89
io_data[7] <= i~88
io_data[8] <= i~87
io_data[9] <= i~86
io_data[10] <= i~85
io_data[11] <= i~84
io_data[12] <= i~83
io_data[13] <= i~82
io_data[14] <= i~81
io_data[15] <= i~80
i_address[0] => Mux_128.IN5
i_address[0] => Mux_130.IN5
i_address[0] => Mux_132.IN5
i_address[0] => Mux_134.IN5
i_address[0] => Mux_136.IN5
i_address[0] => Mux_138.IN5
i_address[0] => Mux_140.IN5
i_address[0] => Mux_142.IN5
i_address[0] => Mux_144.IN5
i_address[0] => Mux_146.IN5
i_address[0] => Mux_148.IN5
i_address[0] => Mux_150.IN5
i_address[0] => Mux_152.IN5
i_address[0] => Mux_154.IN5
i_address[0] => Mux_156.IN5
i_address[0] => i~58.IN1
i_address[0] => Mux_159.IN13
i_address[0] => Mux_160.IN3
i_address[0] => Mux_161.IN13
i_address[0] => Mux_162.IN3
i_address[0] => Mux_163.IN3
i_address[0] => Mux_164.IN3
i_address[0] => Mux_165.IN3
i_address[0] => Mux_166.IN3
i_address[0] => Mux_167.IN3
i_address[0] => Mux_168.IN3
i_address[0] => Mux_169.IN3
i_address[0] => Mux_170.IN3
i_address[0] => Mux_171.IN3
i_address[0] => Mux_172.IN3
i_address[0] => Mux_173.IN3
i_address[0] => Mux_174.IN3
i_address[0] => Mux_175.IN3
i_address[0] => Mux_176.IN3
i_address[0] => Mux_177.IN3
i_address[0] => Mux_221.IN15
i_address[1] => Mux_128.IN4
i_address[1] => Mux_130.IN4
i_address[1] => Mux_132.IN4
i_address[1] => Mux_134.IN4
i_address[1] => Mux_136.IN4
i_address[1] => Mux_138.IN4
i_address[1] => Mux_140.IN4
i_address[1] => Mux_142.IN4
i_address[1] => Mux_144.IN4
i_address[1] => Mux_146.IN4
i_address[1] => Mux_148.IN4
i_address[1] => Mux_150.IN4
i_address[1] => Mux_152.IN4
i_address[1] => Mux_154.IN4
i_address[1] => Mux_156.IN4
i_address[1] => Mux_159.IN12
i_address[1] => Mux_160.IN2
i_address[1] => Mux_161.IN12
i_address[1] => Mux_162.IN2
i_address[1] => Mux_163.IN2
i_address[1] => Mux_164.IN2
i_address[1] => Mux_165.IN2
i_address[1] => Mux_166.IN2
i_address[1] => Mux_167.IN2
i_address[1] => Mux_168.IN2
i_address[1] => Mux_169.IN2
i_address[1] => Mux_170.IN2
i_address[1] => Mux_171.IN2
i_address[1] => Mux_172.IN2
i_address[1] => Mux_173.IN2
i_address[1] => Mux_174.IN2
i_address[1] => Mux_175.IN2
i_address[1] => Mux_176.IN2
i_address[1] => Mux_177.IN2
i_address[1] => Mux_221.IN14
i_address[2] => Mux_159.IN11
i_address[2] => Mux_160.IN1
i_address[2] => Mux_161.IN11
i_address[2] => Mux_162.IN1
i_address[2] => Mux_163.IN1
i_address[2] => Mux_164.IN1
i_address[2] => Mux_165.IN1
i_address[2] => Mux_166.IN1
i_address[2] => Mux_167.IN1
i_address[2] => Mux_168.IN1
i_address[2] => Mux_169.IN1
i_address[2] => Mux_170.IN1
i_address[2] => Mux_171.IN1
i_address[2] => Mux_172.IN1
i_address[2] => Mux_173.IN1
i_address[2] => Mux_174.IN1
i_address[2] => Mux_175.IN1
i_address[2] => Mux_176.IN1
i_address[2] => Mux_177.IN1
i_address[2] => Mux_221.IN13
i_address[3] => Mux_159.IN10
i_address[3] => Mux_160.IN0
i_address[3] => Mux_161.IN10
i_address[3] => Mux_162.IN0
i_address[3] => Mux_163.IN0
i_address[3] => Mux_164.IN0
i_address[3] => Mux_165.IN0
i_address[3] => Mux_166.IN0
i_address[3] => Mux_167.IN0
i_address[3] => Mux_168.IN0
i_address[3] => Mux_169.IN0
i_address[3] => Mux_170.IN0
i_address[3] => Mux_171.IN0
i_address[3] => Mux_172.IN0
i_address[3] => Mux_173.IN0
i_address[3] => Mux_174.IN0
i_address[3] => Mux_175.IN0
i_address[3] => Mux_176.IN0
i_address[3] => Mux_177.IN0
i_address[3] => i~68.IN0
i_address[3] => i~69.IN0
i_address[3] => i~72.IN0
i_address[3] => i~73.IN0
i_address[3] => i~75.IN0
i_address[3] => Mux_221.IN12
i_ep_wr => i~55.IN0
i_ep_rd => i~56.IN0
i_ep_rd => i~21.OUTPUTSELECT
i_ep_rd => i~22.OUTPUTSELECT
i_ep_rd => i~23.OUTPUTSELECT
i_ep_rd => i~24.OUTPUTSELECT
i_ep_rd => i~25.OUTPUTSELECT
i_ep_rd => i~26.OUTPUTSELECT
i_ep_rd => i~27.OUTPUTSELECT
i_ep_rd => i~28.OUTPUTSELECT
i_ep_rd => i~29.OUTPUTSELECT
i_ep_rd => i~30.OUTPUTSELECT
i_ep_rd => i~31.OUTPUTSELECT
i_ep_rd => i~32.OUTPUTSELECT
i_ep_rd => i~33.OUTPUTSELECT
i_ep_rd => i~34.OUTPUTSELECT
i_ep_rd => i~35.OUTPUTSELECT
i_ep_rd => i~36.OUTPUTSELECT
io_had[0] <= i~111
io_had[1] <= i~110
io_had[2] <= i~109
io_had[3] <= i~108
io_had[4] <= i~107
io_had[5] <= i~106
io_had[6] <= i~105
io_had[7] <= i~104
io_had[8] <= i~103
io_had[9] <= i~102
io_had[10] <= i~101
io_had[11] <= i~100
io_had[12] <= i~99
io_had[13] <= i~98
io_had[14] <= i~97
io_had[15] <= i~96
o_ha16 <= i~77.DB_MAX_OUTPUT_PORT_TYPE
i_hp_wr => i~3.IN0
i_hp_wr => i~1.OUTPUTSELECT
i_hp_wr => i~2.OUTPUTSELECT
i_hp_wr => i~37.OUTPUTSELECT
i_hp_wr => i~38.OUTPUTSELECT
i_hp_wr => i~39.OUTPUTSELECT
i_hp_wr => i~40.OUTPUTSELECT
i_hp_wr => i~41.OUTPUTSELECT
i_hp_wr => i~42.OUTPUTSELECT
i_hp_wr => i~43.OUTPUTSELECT
i_hp_wr => i~44.OUTPUTSELECT
i_hp_wr => i~45.OUTPUTSELECT
i_hp_wr => i~46.OUTPUTSELECT
i_hp_wr => i~47.OUTPUTSELECT
i_hp_wr => i~48.OUTPUTSELECT
i_hp_wr => i~49.OUTPUTSELECT
i_hp_wr => i~50.OUTPUTSELECT
i_hp_wr => i~51.OUTPUTSELECT
i_hp_wr => i~52.OUTPUTSELECT
i_hp_wr => i~54.IN0


|host_2191|ep_sm:U2
i_reset => state~1.IN1
i_clock => state~0.IN1
i_start => i~1.IN0
i_start => i~2.IN0
i_finish_ep_access => i~4.IN0
i_finish_ep_access => i~7.IN0
o_ack <= ack_asserted.DB_MAX_OUTPUT_PORT_TYPE


|host_2191|hp_sm:U3
i_reset => state~1.IN1
i_clock => state~0.IN1
i_start => i~0.IN0
i_start => i~2.IN0
i_host_cycle => i~11.IN0
i_host_cycle => Select_73.IN2
i_host_cycle => Select_85.IN2
i_host_mem_sel => i~23.IN0
i_host_mem_sel => i~24.IN0
i_host_strobe => i~26.IN0
i_host_strobe => i~18.DATAB
i_host_strobe => i~27.IN0
o_latch_had <= Select_141.DB_MAX_OUTPUT_PORT_TYPE
o_sm_finished <= Select_143.DB_MAX_OUTPUT_PORT_TYPE
i_hack => i~12.IN0
i_hack => i~18.OUTPUTSELECT
i_hack => i~20.OUTPUTSELECT
o_hcms <= Select_126.DB_MAX_OUTPUT_PORT_TYPE
o_hcioms <= Select_129.DB_MAX_OUTPUT_PORT_TYPE
o_hale <= Select_132.DB_MAX_OUTPUT_PORT_TYPE
o_hwr <= Select_135.DB_MAX_OUTPUT_PORT_TYPE
o_hrd <= Select_138.DB_MAX_OUTPUT_PORT_TYPE


|host_2191|watchdog:U4
i_clock => wd_restart.CLK
i_clock => wd_expired.CLK
i_clock => wd_counter_counter_value[22].CLK
i_clock => wd_counter_counter_value[21].CLK
i_clock => wd_counter_counter_value[20].CLK
i_clock => wd_counter_counter_value[19].CLK
i_clock => wd_counter_counter_value[18].CLK
i_clock => wd_counter_counter_value[17].CLK
i_clock => wd_counter_counter_value[16].CLK
i_clock => wd_counter_counter_value[15].CLK
i_clock => wd_counter_counter_value[14].CLK
i_clock => wd_counter_counter_value[13].CLK
i_clock => wd_counter_counter_value[12].CLK
i_clock => wd_counter_counter_value[11].CLK
i_clock => wd_counter_counter_value[10].CLK
i_clock => wd_counter_counter_value[9].CLK
i_clock => wd_counter_counter_value[8].CLK
i_clock => wd_counter_counter_value[7].CLK
i_clock => wd_counter_counter_value[6].CLK
i_clock => wd_counter_counter_value[5].CLK
i_clock => wd_counter_counter_value[4].CLK
i_clock => wd_counter_counter_value[3].CLK
i_clock => wd_counter_counter_value[2].CLK
i_clock => wd_counter_counter_value[1].CLK
i_clock => wd_counter_counter_value[0].CLK
i_clock => wd_count.CLK
i_reset => wd_restart.ACLR
i_reset => wd_expired.ACLR
i_reset => wd_counter_counter_value[22].ACLR
i_reset => wd_counter_counter_value[21].ACLR
i_reset => wd_counter_counter_value[20].ACLR
i_reset => wd_counter_counter_value[19].ACLR
i_reset => wd_counter_counter_value[18].ACLR
i_reset => wd_counter_counter_value[17].ACLR
i_reset => wd_counter_counter_value[16].ACLR
i_reset => wd_counter_counter_value[15].ACLR
i_reset => wd_counter_counter_value[14].ACLR
i_reset => wd_counter_counter_value[13].ACLR
i_reset => wd_counter_counter_value[12].ACLR
i_reset => wd_counter_counter_value[11].ACLR
i_reset => wd_counter_counter_value[10].ACLR
i_reset => wd_counter_counter_value[9].ACLR
i_reset => wd_counter_counter_value[8].ACLR
i_reset => wd_counter_counter_value[7].ACLR
i_reset => wd_counter_counter_value[6].ACLR
i_reset => wd_counter_counter_value[5].ACLR
i_reset => wd_counter_counter_value[4].ACLR
i_reset => wd_counter_counter_value[3].ACLR
i_reset => wd_counter_counter_value[2].ACLR
i_reset => wd_counter_counter_value[1].ACLR
i_reset => wd_counter_counter_value[0].ACLR
i_reset => wd_count.ACLR
i_start => i~1.IN0
i_start => i~58.IN0
o_error <= i~0.DB_MAX_OUTPUT_PORT_TYPE


|host_2191|rising_edge:U5
i_clock => o_output~reg0.CLK
i_clock => edge_detection_old_value.CLK
i_reset => i~2.IN0
i_reset => i~4.IN0
i_reset => o_output~reg0.ACLR
i_input => i~1.IN0
i_input => i~2.IN1
i_input => i~3.IN0
i_input => edge_detection_old_value.DATAIN
o_output <= o_output~reg0.DB_MAX_OUTPUT_PORT_TYPE


